Method of forming an opening or cavity in a substrate for receiving an electronic component

ABSTRACT

A method of forming an opening or cavity in a substrate, for receiving an electronic component, consists of or includes providing a patterned opaque masking layer on or adjacent a first major surface of the substrate, the masking layer having an opening overlying the position where the cavity is to be made, removing material from the substrate by laser ablation through the opening thereby forming an opening or cavity of a suitable size for receiving said electronic component.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.10/204,154, filed Mar. 24, 2003, which is here incorporated by referencein its entirety.

BACKGROUND OF THE INVENTION

This invention relates to a method of forming an opening or cavity in asubstrate. The substrate is preferably of the type which can include anelectronic component or integrated circuit. An example of such asubstrate is a printed circuit board (PCB).

As circuit density of electronic components, particularly integratedcircuits, has increased, there has been a corresponding increase in theproblems associated with connecting them to connections and conductorson printed circuit boards (PCB). This problem is particularly severewhen there are a large number of interconnects, (for example in the caseof micro-processor devices).

PRIOR ART

Known soldering and wire bonding techniques are expensive and requirecumbersome equipment in order to achieve efficiency in the fabricationprocess. Additionally there may be a requirement to heat the soldertwice; firstly on preparation of the PCB and again when mountingcomponents on the PCB

The technique of forming an opening in a substrate for an electroniccomponent is well known, see for example U.S. Pat. No. 3,480,836, whichdiscloses pre-punching holes in a substrate, after which conductor leadshaving tabs which project over the cavity are attached. This techniquehas been further developed, for example in U.S. Pat. No. 4,927,491 inwhich the substrate is a flexible tape.

JP 10098081 discloses using a carbon gas laser to cut a perimeter trenchfor an opening in a substrate having a copper foil laminated on bothsides, the remaining substrate material being removed in a second step.The copper foil is then patterned by lithography and etching to formleads to retain a component.

SUMMARY OF THE INVENTION

The present invention arose in order to provide smaller interconnectdimensions on a PCB, thereby rendering it capable of being producedthinner and eliminating the need for synthetic plastics leaded chipcarriers (PLCCs). The present invention can also be used to manufacturechip carriers with beneficial properties and lower cost.

According to a first aspect of the present invention there is provided amethod as specified in claims 1-8. According to a second aspect of theinvention there is provided a substrate as specified in claim 9.According to a further aspect the invention provides a device asspecified in claim 10.

Embodiments of the invention will now be described, by way of exampleonly, with reference to the accompanying schematic Figures in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a diagrammatic view of an embodiment of an apparatus forforming interconnects on a substrate;

FIGS. 2 a and 2 b are diagrammatic sectional and plan views of a singlecomponent mounted on the substrate produced using the apparatus of FIG.1;

FIGS. 3 a to 3 c are plan views showing examples of interconnects; and

FIG. 4 shows a method of forming a contact through a via hole.

DETAILED DESCRIPTION OF CERTAIN ADVANTAGEOUS EMBODIMENTS

FIG. 1 is an overall view of an apparatus 10 for forming interconnectson a substrate 12. The apparatus 10 includes a laser 14, focussedthrough a suitable lens system 16, which in use, reflects off mirror 18.In the present embodiment a CO.sub.2 laser having a power of 50-500Watts and a beam diameter of 480 microns is used. However, higher powersand larger diameters are desirable for increasing throughput. An Excimerlaser or YAG laser can be used as an alternative.

So as to be able to fully appreciate the apparatus it is necessary toconsider the apparatus in association with other equipment. Theseinclude means for delivering the substrate, such as a flat bed table 24.Means for selectively removing regions from a first layer of material.This may include a photo imager (not shown) and an etch bath (notshown). Means for removing volumes of the substrate may be a laser 14 oran ion beam etching device (not shown) or a plasma etcher (not shown).Means for removing the material from the second surface, may be amodified etch bath capable of etching an electrical conductor. These inconjunction with the apparatus are controlled by a series ofmicro-processors (not shown).

Power output of the laser 14 is controlled by micro-processor 20. Aswell as controlling the pulse duration and energy of the laser 14,micro-processor 20 orientates mirror 18 and may also be used to focusthe laser 14 via the lens system 16.

A different depth cavity can be formed either by pulsing a larger numberof pulses from the energy source or increasing the duration of eachpulse. Similarly an array of cavities can be fabricated, the number andsize of cavities in the array can be varied to produce differentproducts or accommodate different devices.

Substrate 12, shown in greater detail in FIG. 2, is in the form of alaminated sheet or tape. Two layers 21 a and 21 b of metallic material,such as copper (or aluminium), sandwich a flexible substrate 12comprises an etchable polymer such as polyethylene (tri-thalmate) (PET).As substrate 12 is flexible it is delivered on rolls or drums 22 a. Assubstrate 12 is flexible, after it has been connected with componentsthe substrate, including components, can be wound onto another roll 22b.

In the present embodiment the thickness of the substrate is 190 microns,although thicknesses between 100 microns and 600 microns have beenemployed. Ideally if a silicon chip is to be inserted, it will be grounddown from the back to give a similar thickness to that of the substrate.Alternatively, a substrate thickness is chosen according to thethickness of the semiconductor chip.

A non-metallic base material such as PET substrate 12 is clad with ametal material on at least one of its surfaces by laminating a sheet ofthe metal material, using an adhesive bonding agent or by catalysing thebase material and plating a layer of metal which coats the base materialin uniform thickness.

Substrate 12 may be introduced in a part finished or ‘raw’ form. If itis raw, the substrate needs to be treated. This is achieved by firstlycoating the substrate with a photoresist. This may be applied as acurtain coat by thin uniform spraying, or using other known techniques.

Conductor tracks, interconnects and die bonding sites are thenphoto-imaged on both surfaces. This is a routine step in printed wiringboard processing.

Using the photo image and etch procedure, a circuit pattern is formed onthe metal clad surface of the substrate. The circuit pattern hasattachment locations 52 which correspond to bond pad dimensions andlocations of a semiconductor component (not shown) to be inserted intothe cavity defined on the substrate and connected to interconnects.

On the side of the material opposing the circuit pattern, at an areacorresponding to the dimensions of the semiconductor component to bemounted, there are located corresponding bonding pads of the circuitpattern.

Once a region from the upper material has been removed, laser ablationremoves the underlying polymer layer defining the substrate. Althoughmention has been made of PET as the polymer used in the substrate, avariety of other materials are suitable for use. For example, liquidcrystal polymers (LCPs), polyamide, PEN/polyethylene napa thalmate, polyvinyl chloride and Mylar (Trademark) can be incorporated into or fromthe substrate. Another suitable material for fabricating chip carriersis Thermount (Trademark)—available from Dupont—a random strand aramidreinforced laminate material, although this material has poor edgeprofiling properties it is a very easy material to ablate.

Laser ablation occurs at extremely high rates, typically between 300 to800 pulses per second. Micro-processor 20 varies the rate and durationof pulses from laser 14. This combination permits the vaporisation rateto be controlled and administered for the specific properties of thesubstrate material. The result is that ablation occurs at a precise Xand Y location over a known area to a predetermined depth for a givenarray of M rows of cavities by N columns of cavities, defined over aspecific area.

Events in the production process are modular. The substrate is firstlycoated, then photo-imaged. Etching and stripping then occur. Laserablation of the opening or cavity is then performed. The next step isplasma and/or wet chemical cleaning using for example a potassiumpermanganate solution. After this cleaning step, metal is deposited onthe mechanical tab structures such (or contacts) just formed. This isachieved by immersion alloy deposition from solution. This is anelectrodeless process, although electroplating could be used as analternative. The metal alloy chosen must be compatible with theapplication or bonding method chosen. Typical materials include tin,gold or silver based materials.

During the laser ablation step, material ablated from the cavity canredeposit on other parts of the substrate. Such deposits are usuallyremoved during the plasma and/or wet cleaning step. However, if thematerial being ablated is polyimide removal can be difficult. To aidremoval, an optional sacrificial layer can be deposited on the substratesurface or surfaces prior to the laser ablation step. The sacrificiallayer can be photoresist for example. After ablation this layer can beeasily removed by plasma and/or wet cleaning, and any redepositedmaterial is removed at the same time.

The PCBs are then cut to shape and finished. This contouring step can beachieved by CNC routing, die punching, or YAG laser contouring.

Electrodes are pre-defined by the etching process. A series of digitatedconnectors, spaced one from another and arranged to be in register withcontacts of the component or die to be inserted into the cavity or dieare formed by a metal etch process before laser ablation of thedielectric. As an alternative, the electrodes can be laser etched in themetal layer at the base of the cavity after the dielectric material hasbeen ablated. Alternatively, modifications to a pre-etched pattern inthis layer can be made with the laser after the cavity has been formed(for example by removing tabs to free the end of an elongate structure).

The perforated substrate with contacts defined on one surface acts as ashelved recess for receiving electronic components (50). The simplestembodiment is an embodiment with one or two contacts, suitable forreceiving, for example, capacitors (FIG. 3 a). Transistors require athird contact to be formed and a sketch of such is shown in FIG. 3 b.More complex devices, such as integrated circuits (ICs), Read OnlyMemory (ROM), Random Access Memory (RAM) or micro-processors requiremany contacts (51). An example is shown in FIG. 3 c.

The elongate metal bond leads or tabs which form the electrical contactsperform a dual function. Firstly, they act as electrical pathwaysto/from components. Secondly, they retain components at least during thefabrication process, due to their mechanical properties. For example,devices can be compression mounted, where insertion of the device causesthe projecting tabs to fold, creating resilient clip structures whichkeep the device in place. It has been found that silver coated contacttabs are particularly advantageous in this application.

Registration of each etched region, on each surface is crucial. However,it will be appreciated that a certain degree of tolerance is permittedand die locations may be offset so as to provide for a suitablemechanical recess, capable of receiving and holding electricalcomponents.

Components can be bonded to the electrodes projecting adjacent thecavity by for example ultrasonic bonding and/or pressure bonding.Alternatively shrink-wrap films can be adapted to urge a componentagainst the electrodes, or an adhesive tape or tab may be used.

The invention may be used to create an array of cavities. An advantageof this arrangement is that a plurality of devices may be produced on asingle substrate.

The substrate may be flexible, and capable of being wound or folded soas to ease transportation by reducing its bulk. For example, eitherprior to and/or after fabrication, the substrate may be stored on aspool.

Components may be introduced into previously formed cavities by anyknown technique, such as for example a pick-and-place machine, by airjet (vacuum) or by hand. An arrangement whereby a reduced air pressureis created at one surface is particularly convenient. The pressuredifference draws electronic components into each cavity, so that thecomponent (such as a semiconductor chip or die) may be bonded to thesubstrate.

If the present invention is used to make chip carrier circuitry,individual chip carriers may be die cut, routed, or sawn from arelatively large sheet or tape of the substrate.

A particularly advantageous feature of the invention is that itfacilitates a flatter chip carrier profile than is normally achievable.Typically thickness of a chip carrier is fabricated in accordance withthe invention is 17 micron greater than the die thickness. However, byusing the present invention, because a portion of substrate is removedto accept the component, the resultant carrier profile is thinner thanhas been previously achievable.

Many different types of electrical and electronic components can beplaced into the substrate opening or cavity. These include resistors,capacitors, inductors, transistors, integrated circuits, tuners,wave-guides, piezoelectric devices, coils and/or heat-sinks.Additionally, or alternatively, each opening or cavity may be adapted toreceive an electro-optical device, such as a liquid crystal device or alight emitting diode. In this latter case conductive tracks may bedefined on a surface, using a transparent material such as Indium TinOxide (ITO).

In the above embodiments, the opening formed by laser ablation hasextended all the way through the substrate. As an alternative a blankopening or cavity may be fabricated by stopping the ablation before allthe substrate is removed. This technique is useful for making cavitiesin multilayer PCBs.

Multilayer PCBs have prepreg dielectric layers, typically 70 micronsthick, interleaved with conductive metal layers. The laser ablationprocess can be used to remove such material to expose bond pads in asubsurface metal layer. A flip chip die with solder bumps can then beplaced on top of the bond pads, so that when the assembly is heated thesolder flows and bonds the chip in place. An advantage of this techniqueis that the subsurface layers of the multilayer PCB can be used forsignal input and output to the chip, which shortens the signal conductorlength and reduces propagation delays.

In addition to the formation of openings or cavities for mountingsemiconductor or other devices, it is also possible to ablate via holesthrough the PCB at the same time. In a preferred embodiment, shown inFIG. 4, an elongate flap or tab of metal (30) is left at the bottom ofthe via hole (31). This flap or tab is longer than the depth of the viahole, and can optionally have an end shaped to form a serrated edge (32)or a barb or spike. This flap or tab can be urged into the via byblowing a gas or liquid towards the via, or by pushing using a pin orsimilar solid tool. The part of the flap or tab projecting though theother side of the via hole can then be crimped to a conductive track atthe other side of the PCB, forming a through contact without the usualplating steps. In FIG. 4 the serrated edges are shown engaging with asecond opening or cavity (33) in the substrate, which can be formed bylaser ablation or otherwise. This technique may also be advantageous inconventional PCB manufacture, when openings or cavities for receivingelectronic devices are not cut in the substrate.

Although in the above embodiment the laser ablation occurs through apatterned metal layer carried by the substrate, it is possible to use aseparate metal sheet with corresponding holes cut therein as a maskpositioned adjacent the substrate as an alternative.

In the above examples, the laser ablation step exposed elongate contactswhich projected into the resulting cavity. Such elongate metal membersneed not be electrical contacts, however—they can form mechanicalstructures such as for example for pressure switches.

The invention has been described by way of examples only and variationmay be made to the embodiments described, for example by usingequivalents not specifically disclosed.

Finally, the document from which this application claims priority,especially the Figures, is incorporated herein by reference.

1. A method of making a substrate to receive an electronic comprisingthe steps of
 1. providing a laminated dielectric substrate ofpredetermined thickness having a first and second side and beingcomprised of a dielectric substrate material laminated with a conductivefoil of a prescribed thickness on both the first and second sides; 2.creating a conductive circuit on the second side of the laminateddielectric substrate by selectively removing portions of the conductivefoil on the second side of the laminated dielectric substrate to leaveremaining a conductive foil circuit projecting in part into theperimeter of a preselected volume of the dielectric substrate materialat a prescribed location within the perimeter;
 3. removing conductivefoil from the first side of the laminated dielectric substrate withinthe perimeter of the preselected volume to expose the dielectricsubstrate material completely within said perimeter;
 4. removingentirely the volume of the dielectric substrate material within saidperimeter to create a void in the dielectric substrate material withoutdamaging the part of the conductive circuit projecting into theperimeter of the void; whereby an electronic component having at leastone contact on the surface of the electronic component first insertedinto the void, can be inserted into the void of the dielectric substratematerial, from the first side of the laminated dielectric substrate withthe at least one contact corresponding in position to the part of saidconductive circuit that projects into the perimeter of the void so thatwhen fully inserted, the contact on the electronic component registerswith and contacts said projecting part of the interconnecting conductivecircuit; whereupon the contact on the electronic component and theprojecting part of the conductive circuit can be bonded together to holdthe electronic component in the void of the dielectric substratematerial.
 2. A method according to claim 1 wherein step 4 is carried outby a laser.
 3. A method according to claim 2 wherein the laminateddielectric substrate is move past the laser.
 4. A method according toclaim 1 wherein the laser is a CO₂ laser.
 5. A method according to claim1 wherein step 2 is carried out using artwork,
 6. A method according toclaim 1 wherein the conductive foil is one of copper and aluminum.
 7. Amethod according to claim 6 wherein the conductive foil is copper.
 8. Amethod according to claim 1 wherein the dielectric material is apolymer.
 9. A method according to claim 8 wherein the polymer is one ofPET, liquid crystal polymers, polyamide, PEN, polyvinyl chloride, Mylar,and Thermount, a random strand aramid.
 10. A method according to claim 9wherein the polymer is PET.
 11. A method according to claim 1 whereinthickness of the substrate is less than 200 microns.
 12. A methodaccording to claim 1 wherein step 2 includes creating conductor tracks.13. A method according to claim 1 wherein step 2 creates a plurality ofconductive tabs projecting into the perimeter of the void.
 14. A methodaccording to claim 1 wherein the perimeter of the void matches theelectronic component to be mounted.
 15. A method according to claim 3wherein the laser is pulsed at a relatively high rate.
 16. A methodaccording to claim 15 wherein the rate is from about 300 to about 800pulses per second.
 17. A method according to claim 1 wherein step 4 isfollowed by plasma or wet chemical cleaning.
 18. A method according toclaim 1 wherein the projecting part of the interconnecting circuit isused as a pressure switch.
 19. A method according to claim 1 whereinstep 4 is carried out to create a plurality of spaced voids.
 20. Amethod according to claim 19 wherein the spaced voids are arranged in anarray.
 21. A method according to claim 1 wherein step 4 is followed bydeposition of one of tin, silver and gold on the part of theinterconnecting circuit projecting into the perimeter of the void.
 22. Amethod according to claim 21 wherein the deposition covers all exposedportions of the laminated dielectric substrate.
 23. A method accordingto claim 1 wherein the electronic component is a die.
 24. A method claim1 wherein the electronic component is a semiconductor chip.
 25. A methodaccording to claim 24 wherein the semiconductor chip to be mounted inthe substrate is one of an IC, ROM, RAM and microprocessor.
 26. Aaccording to claim 1 wherein the bonding of the electronic component tobe mounted in the substrate can be carried out by one of ultrasonicbonding and pressure bonding.
 27. A method according to claim 1 whereinthe laminated dielectric substrate is flexible.
 28. A method accordingto claim 27 wherein step 4 is followed by winding the laminateddielectric substrate on a spool.
 29. A method according to claim 1wherein the mounting of an electronic component can be carried out usingone of a pick-and-place machine, an air jet and a vacuum.
 30. A methodaccording to claim 1 wherein the laminated dielectric substrate is oneof a tape and a sheet.
 31. A method according to claim 1 wherein step 4is followed by repeating steps 1 to 4 one or more times so that aplurality of separate electronic component interconnected devices can bemounted in a substrate, followed by stacking the separate substrates tocreate a multilevel structure.
 32. A method according to claim 1 whereinthe electronic component to be mounted in the substrate is one of aresistor, a capacitor, an inductor, a diode, a transistor, an IC, atuner, a wave guide, a piezoelectric device, a coil, a heat sink, anelectro-optical device.
 33. A method according to claim 32 wherein theelectronic component can be an LED.
 34. A method according to claim 33wherein conductive tracks are created on the laminated dielectricsubstrate that interconnect the LED when mounted in the substrate.
 35. Amethod according to claim 34 wherein the tracks are transparent andcomposed of indium tin oxide.
 36. A method according to claim 31 whereina preselected portion of an exposed conductive foil is removed to exposethe underlying dielectric substrate material, creating a void in theunderlying material exposed and exposing an embedded conductive foil sothat a flip chip die can be inserted into the void to contact theexposed embedded conductive foil, and bonded thereto.
 37. A methodaccording to claim 36 wherein the flip chip die to be mounted caninclude solder bumps to effect bonding.
 38. A method of making asubstrate to include a connection from one side to the other comprisingthe steps of
 1. providing a laminated dielectric substrate ofpredetermined thickness having a first and second side and beingcomprised of a dielectric substrate material laminated with a conductivefoil of a prescribed thickness on both the first and second sides; 2.creating a conductive circuit on at least one side of the laminateddielectric substrate;
 3. creating an interconnecting conductive circuitby selectively removing portions of the conductive foil on the secondside of the laminated dielectric substrate to leave remaining anelongated interconnecting tab in electrical contact with the conductivefoil on the second side of the laminated dielectric substrate, the tabhaving a free end and being longer than the predetermined thickness ofthe substrate, the free end of the tab projecting into the perimeter ofa preselected volume of the dielectric substrate material;
 4. removingconductive foil from the first side of the laminated dielectricsubstrate within the perimeter of the preselected volume to expose thedielectric substrate material completely within said perimeter; 5.removing entirely the volume of the dielectric substrate material withinsaid perimeter to create a void in the dielectric substrate materialwithout damaging the elongated interconnecting tab projecting into theperimeter of the void;
 6. moving the free end of the tab through thevoid to the first side of the laminated dielectric substrate; and 7.connecting the tab to the conductive foil on the first side of thelaminated dielectric substrate.
 39. A method according to claim 38wherein step 5 is carried out by a laser.
 40. A method according toclaim 39 wherein the laminated dielectric substrate is move past thelaser.
 41. A method according to claim 38 wherein the laser is a CO₂laser.
 42. A method of according to claim 38 wherein step 3 is carriedout using artwork
 43. A method according to claim 38 wherein theconductive foil is one of copper and aluminum.
 44. A method according toclaim 38 wherein the dielectric material is a polymer.
 45. A methodaccording to claim 38 wherein step 5 is followed by deposition of one oftin, silver and gold on the tab projecting into the perimeter of thevoid
 46. A method according to claim 45 wherein the deposition coversall exposed portions of the laminated dielectric substrate.
 47. Anelectronic interconnecting device comprising;
 1. a laminated dielectricsubstrate of predetermined thickness having a first and a second sideand being comprised of a polymer material laminated with a conductivefoil on both the first and second sides;
 2. a circuit formed in the foilon the second side of the laminated substrate having at least oneconductive foil part projecting into the perimeter of a void in thedielectric material at a prescribed location within the perimeter;whereby an electronic component having a thickness not greater than thepreselected thickness of the substrate can be positioned in the void ofthe laminated substrate and having at least one contact on its surfaceof the electronic component corresponding in position to, registeringwith and contacting the at least one conductive foil part, and be bondedto the at least one conductive foil part to hold the component in thevoid.
 48. A substrate according to claim 47 wherein the foil is composedof copper.
 49. A substrate according to claim 47 wherein the dielectricmaterial is PET.
 50. A substrate according to claim 47 wherein thepredetermined thickness is less than 200 microns.
 51. A substrateaccording to claim 47 wherein the circuit formed in the foil includeconductor tracks.
 52. A substrate according to claim 47 wherein aplurality of conductive foil parts projecting into the perimeter of thevoid in the dielectric material at a prescribed location within theperimeter.
 53. A substrate according to claim 47 wherein the perimeterof the electronic component registers with the perimeter of the void.54. A substrate according to claim 47 wherein the laminated dielectricsubstrate is one of a tape and sheet.
 55. A substrate according to claim54 wherein the substrate contains a plurality of voids with circuitformed in the foil associated with each void and within each void ismounted an electronic component.
 56. A substrate according to claim 55wherein plurality of voids are arranged as an array.
 57. A substrateaccording to claim 47 wherein the interconnecting conductive foil partprojecting into the perimeter of a void in the dielectric material at aprescribed location within the perimeter is coated with one of silverand gold.
 58. A substrate according to claim 47 wherein a plurality ofsuch substrates are stacked together.
 59. A substrate according to claim47 wherein the final geometry of the substrate with the electroniccomponent mounted in the void is planar.
 60. A substrate having aconnection from one side to the other comprising;
 1. a laminateddielectric substrate of predetermined thickness having a first andsecond side and being comprised of a dielectric substrate materiallaminated with a conductive foil on both the first and second sides; 2.an electric circuit on at least one side of the laminated dielectricsubstrate;
 3. a conductive connection for the electric circuit formed byselectively removal of portions of the conductive foil on the secondside of the laminated dielectric substrate to leave an elongatedinterconnecting tab in electrical contact with the conductive foil onthe second side of the laminated dielectric substrate, the tab having afree end and being longer than the predetermined thickness of thesubstrate, the free end of the tab projecting into the perimeter of apreselected volume of the dielectric substrate material;
 4. conductivefoil being absent on the first side of the laminated dielectricsubstrate within the perimeter of the preselected volume;
 5. a voidcreated in the dielectric substrate material within said perimeter; 6.the free end of the elongated interconnecting tab passing through thevoid to the first side of the laminated dielectric substrate; andconnected to the conductive foil on the first side of the laminateddielectric substrate.
 61. A substrate according to claim 60 wherein theconductive foil is one of copper and aluminum.
 62. A substrate accordingto claim 60 wherein the dielectric material is a polymer.
 63. Asubstrate according to claim 60 wherein the tab is coated with one oftin, silver and gold
 64. A substrate according to claim 63 wherein allexposed portions of the laminated dielectric substrate are coated.